10 TIPS TO GAIN MAXIMUM PERFORMANCE FROM DELAY LINES

Dennis Fitzsimmons
Engineering Manager, Engineered Components Company
San Luis Obispo, California

Delay lines, those compact discretes that manage to pack a cabinet-full of utility into a package the size of a cufflink, are currently enjoying a renaissance of use, thanks to increased demands in digital signal processing and similar applications, in telecommunications and other industries.

For as long as they have been on the design-engineering scene, delay line products have continually delivered a cost-effective solution for a myriad of timing needs -- adjusting or normalizing circuit timing, providing fixed or programmable pulses from various pulse width inputs, supplying instant-startup clocks or multiple clock cycles during a single master clock cycle, filtering out digital spikes, or decoding Manchester data streams. With so much to offer, it's no surprise that the subtleties of designing and specifying delay lines into specific circuit applications can be somewhat confusing.

Following are ten important considerations to which engineers can refer in order to ensure optimal incorporation of delay lines into their circuits. Just as important, these pointers may help avoid missed delivery dates due to application errors.

1. BE AWARE OF THE DIFFERENCE BETWEEN PASSIVE AND ACTIVE DELAY LINES.

Passive delay lines are less well known and understood than their active counterparts. Passive delay lines are made up of capacitors and inductors and are intended for use in analog applications. With these passive components, a design engineer must be concerned with driving the line, providing the correct termination (or pick-off) of the signal, and compensating for line attenuation.

In addition, active delay lines are digital, incorporating integrated circuits within their package. Thus, the inputs and outputs are already interfaced and characterized for a particular logic family -- TTL, ECL and CMOS.

2. BE SURE TO CONSIDER FREQUENCY CONSTRAINTS IN PASSIVE DESIGNS.

A passive delay line is designed for a specific frequency application. Input pulse rise time must always be faster than the specified output rise time of any line, in order to realize its maximum capabilities. However, delay lines can be used outside of their specified frequency with the following considerations: 1) The higher the frequency, the more overshoot and distortion; 2) conversely, a lower frequency creates less overshoot and distortion; 3) both delay time and rise time may also be adversely affected.

3. DON'T FAIL TO FACTOR IN STRAY CAPACITANCE IN PASSIVE DESIGNS.

The astute design engineer knows to evaluate his or her circuit to determine any impedance mismatching, and any stray inductive or capacitive build-up that may occur in the circuit board by the combination of discreet components. Low impedance delay lines have the characteristic of relatively high capacitive elements in relation to low inductive elements, while high impedance lines have relatively low capacitive elements and high inductive elements.

Consider a short time delay, high impedance delay line with ten taps whose external circuitry adds 2pf per tap, for a total of 20pf of capacitance. This added capacitance will affect delay time accuracy and impedance on the delay line -- in some cases changing delay accuracy or impedance by 20%.

4. SPECIFYING DELAY LINES FOR HIGH FREQUENCIES REQUIRES SPECIAL CONSIDERATIONS.

Engineers occasionally forget that a delay line acts as a multi-pole, low pass filter. This becomes a problem when designers attempt to delay signals with higher frequency characteristics than the delay line is capable of passing. Delay accuracy can change significantly with a change in the input waveform due to variance in the group delay, especially at higher frequencies. The proper specification of a delay line should always include the applied frequency and/or its intended use. Only then can the vendor supply the correct product.

5. AVOID THE "NUMBER ONE" PITFALL WHEN SPECIFYING A DELAY LINE.

Failure to specify the falling edge accuracy is probably the most common omission when specifying a delay line. Many designers wish to maintain a specific pulse width from input to output. In order to maintain the duration of the input pulse width, it is imperative to specify both the rising and falling edge timing accuracy. Standard off-the-shelf delay lines are typically calibrated for rising edge accuracy.

6. DON'T MIX TERMINOLOGY.

Electronic engineers already know that the overall delay time is the time duration between the reference or threshold level of the leading edge of the input pulse, to the reference or threshold level of the leading edge of the output pulse. Analog delay lines are measured at the 50% point of the signal, while digital delay lines use a fixed voltage level, typically the logic threshold voltage.

Additional terms that need to be carefully defined include leading and trailing edges, versus rising and falling edges. "Leading" and "trailing" terminology requires a knowledge of whether the reference pulse is positive or negative. Similarly, any discussion of input frequency often includes references to duty cycle, pulse width and pulse spacing. Again, it is important to ascertain if the pulse is negative or positive. Pulse width is the duration of the pulse itself; pulse spacing is the time between pulses. Rise time (or fall time) is the time required to change from one level to another. In analog lines, the levels are 10% and 90%. Most TTL systems specify levels at 0.8 and 2.0 volts.

7. KNOW THE SIGNIFICANCE OF BUILT-IN "TAPS."

"Taps" provide multiple pick-off points to allow for incremental timing adjustments over the delay line. In a passive (analog) delay line, these taps are simply connections between the inductor/capacitor arrays that are connected to external pins in the package. As many as 20 equally-spaced taps can be included in a single passive package. This flexibility can be useful in circuits where a range of timing is established, but variances in other components need to be compensated for. By jumping to a different tap, circuit timing can be adjusted without having to replace the delay line.

8. REMEMBER THAT, WHEN NECESSARY, DELAY LINES CAN BE FINE TUNED "AFTER THE FACT."

Programmable delay lines can be incorporated where a delay needs to be "dialed in" after assembly, or even where timing needs to be adjusted dynamically. For example, a piece of automated test equipment could vary the timing parameters of the device under test, in order to determine the minimum and maximum timing limits.

9. KNOW THE MAIN ADVANTAGES THAT DELAY LINES HAVE OVER OTHER FREQUENCY-CONTROL COMPONENTS.

Digital delay line products, such as square-wave generators, have certain advantages over crystal-controlled oscillators. Delay line waveform generators can start and stop instantly, allowing them to synchronize to external events. Pixel clock delay lines, for example, can resynchronize at the beginning of each sweep line across a video screen.

Digital square wave generators can take the place of crystals in applications that do not require a crystal's tight frequency control. Delay line waveform generators typically demonstrate 0.5% to 2% frequency
tolerances.

The correction system used in a Digital Frequency Multiplier Module (DFMM) delay line can be used in many situations where a phase-locked loop (PLL) would be incorporated. DFMMs are used in applications where an exact frequency multiple is desired from a given base frequency. Typical uses include clock frequency multiplication when other processes need to be clocked during the main cycle, and code or burst synchronizing where input clocks may be missing one or more edges, but a continuous output clock is required. The synchronizer in the delay line compensates for all phase error at one time, as opposed to the PLL where an error signal gradually shifts the output frequency. As long as the DFMM is used to increase the base frequency no more than five to ten times, the output waveform jitter can be kept to a
minimum.

10. ENSURE THAT THE VENDOR CAN DELIVER NEEDED GOODS ACCORDING TO YOUR TIME SCHEDULE.

Make sure that your vendor is willing to work with you to provide the exact part that is called for, in the exact quantities you need. Many times they can suggest a product that will simplify your circuit. In many cases, an on-shore supplier can deliver parts within four to six weeks, and often sooner if
necessary.

Careful application of the above pointers, before specification, will greatly aid in a delay line vendor's ability to serve the OEM design engineer. The overall result is a finished product that is delivered on time, meets the customer's requirements, and performs as expected in the field.

For more information, call Engineered Components Company, 3580 Sacramento Drive, PO Box 8121, San Luis Obispo, CA 93403-8121, 800-235-4144. Circle 430.