Microsealing

Passivation processing provides wafer-level hermetic protection

A Manufacturing Technology Program within the US Army Aviation and Missile Command (AMCOM) Manufacturing Science and Technology Division is studying a protective semiconductor coating which can provide cost and performance benefits for manufacturers while meeting stringent military requirements for resistance to moisture-induced failures. "The need to replace ceramic-packaged hermetic components is being driven by the high cost of the technology and the rapidly diminishing availability of military-grade components," explains Senior AMCOM Engineer Pete Black. "Component manufacturers are shutting down production of unprofitable military spec devices due to reduced volume demand (currently less than 1% of the total market). The small market is a key reason why commercial semiconductor manufacturers are reluctant to focus on military needs for increased component reliability," he said.

Close-up of a generic die

AMCOM has entered into a cost-shared cooperative agreement with seven organizations to further develop the coating process. Conventional microcircuits use silicon nitride as a passivation material. But, says Black, "the problem with silicon nitride is its susceptibility to pinholes and cracks that make it vulnerable to water vapor intrusion. Also, any impurities within the molding compounds or on the IC can react with the interconnecting metal, using moisture as a catalyst. The result can be corrosion of the interconnected wires and bond pads on the IC, leading to irregular performance and eventual device failure."

The ChipSeal advanced passivation process from Dow Corning, Midland, MI, demonstrates wafer-level hermetic protection to integrated circuits, with bare die reliability that rivals traditional ceramic packaging at a fraction of the cost. The process uses a spun-on coating of FOx flowable oxide to planarize the wafer surface, followed by a sealing top coat of silicon carbide (SiC), produced from Z3MS CVD dielectric material. Openings to the IC contacts are then etched through both layers. The contact pads are covered first with a metal barrier of titanium tungsten (TiW) and then with gold (Au), sealing the etched openings and providing excellent electrical contact. All processes are accomplished using standard semiconductor manufacturing equipment. Figure 1 shows results from the US Air Force's highly accelerated stress testing on bare die in leaded chip carriers, illustrating the high failure rate of standard plastic-encapsulated microcircuits, as compared to devices protected by ChipSeal. A microsection view of the ChipSeal process is shown within the dotted lines in Figure 2.

Figure 1: US Air Force's highly accelerated stress-testing results

The Army concluded that this or similar approaches offer a low-risk solution to military-grade production challenges. "Successful implementation of such a coating system will increase applicability of commercial ICs to harsh military environments with a unit cost near the price of uncoated commercial ICs," says Black. "This will allow Army weapon managers to use lower-cost components for a much broader range of applications. By protecting the IC at the wafer level, the military will also be able to take advantage of smaller, lighter and higher-performing components, such as flip-chip and chip scale packages that were previously unsuitable in non-hermetic form." --SG

For more information:

Circle 706 - Dow Corning, or connect directly to their website via the Online Reader Service Program at http://www.OneRS.net/106df-706

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